(1) Field of the Invention
The present invention relates to a method for making integrated circuits on semiconductor substrates, and more particularly to a method for forming intermetal dielectric (IMD) layers with low dielectric constants (k) to reduce the RC time delays of multilevel wiring for semiconductor integrate circuits. The method is particularly useful for interconnections on ULSI circuits with minimum feature sizes less than 0.25 micrometers (um).
(2) Description of the Prior Art
The fabrication of Ultra Large Scale Integrated (ULSI) circuits on semiconductor substrates requires multi-levels of metal interconnections. The metal interconnections are used to wire up the discrete semiconductor devices, such as field effect transistors (FETs) and bipolar transistors, on semiconductor chips. In more conventional methods, plasma-enhanced chemical vapor deposited (PECVD) silicon oxide (SiO.sub.2) is used as the insulating layer between adjacent metal lines and between the different levels of metal interconnections to electrically insulate the metal lines. The interposed insulating layers have etched via holes which are used to connect one level of metal to the next.
Typically, the silicon oxide (SiO.sub.2) has a relatively high dielectric constant k (relative to vacuum) of about 4.1 to 4.5. However, it is very desirable to reduce the resistance R of the metal lines and the capacitance C between metal lines, since the circuit performance is improved when the RC time constant is reduced. This is particularly important as the device dimensions decrease and the packing density increases, since it is necessary to reduce the spacings between the metal lines in the interconnections to effectively wire up the integrated circuits. Unfortunately, as the spacings between metal lines decrease, the capacitance C increases since the capacitance C is inversely proportional to the spacing d between the lines, where C=ke.sub.O A/d, and where k is the relative dielectric constant, e.sub.O is the permittivity of the free space (vacuum), A is the area, and d is the spacing between lines.
The problem is best exemplified with reference to the schematic cross-sectional view in FIG. 1. Shown is a portion of an insulating layer 12 on a substrate containing semiconductor devices. The substrate and devices are not depicted to simplify the drawings and discussion. A first metal (conductive) layer 14 is patterned to form metal lines 14. A low dielectric constant spin-on polymer 16 (hereafter referred to as a low k polymer) is deposited over and between the first metal lines 14, as an InterMetal Dielectric (IMD) layer 16, and is planarized. An inorganic insulating layer 18, such as SiO.sub.2, is deposited, and via holes are etched in layer 18 and the IMD layer 16. Metal plugs or second level of metal lines are then formed in the via holes to make electrical contact to the first metal lines 14. One of the many via holes 20 having a metal plug 22 is depicted in FIG. 1. A second metal layer 24 is then deposited and patterned to form the second level of metal interconnecting lines 24. As the device minimum feature sizes decrease and the packing density increases, the corresponding spacings d.sub.1 between metal lines 14 used to wire up the devices are also reduced. The capacitance C1 (as depicted in FIG. 1) increases and results in longer RC delay times. Also as the wiring density increases, the capacitance C2 between metal levels (14 and 24) increases because of increased surface area A. Therefore, it is important to use a low k polymer, such as layer 16, to reduce the overall capacitance and to increase circuit speed and to reduce cross talk (coupling) between adjacent metal lines.
Unfortunately, when the via holes are etched in the low k polymer, the exposed polymer is damaged in the via holes during the plasma ashing in oxygen used remove the via hole photoresist etch mask after plasma etching. This damaged portion of the low k polymer (or low k spin-on glass (SOG)) becomes strained resulting in cracking, and becomes much more hygroscopic. Therefore, absorption of moisture of the damaged low k polymer or SOG during exposure to atmosphere later results in unwanted metal corrosion and high contact resistance in the via hole. This problem is best exemplified with reference to the prior art, shown in FIGS. 2 through 4, for forming the conventional low k polymer IMD layer/via hole structure.
As shown in FIG. 2, a first metal layer 14 is deposited and patterned to form metal lines 14 on an insulating layer 12 over the devices formed on a substrate. The substrate having completed semiconductor devices is not depicted to simplify the drawing and discussion. Next, a low k polymer layer 16 is spin-coated, with or without an adhesion/barrier layer 17 (such as a low-temperature PECVD silicon oxide). The low k polymer is cured, and a second IMD layer 18, typically a PECVD SiO.sub.21 is deposited and planarized by chemical/mechanical polishing (CMP). A via hole photoresist mask 30 is formed by conventional means having openings over the first metal lines 14 where via holes in the IMD layers 18 and 16 are required. Now as shown in FIG. 3, anisotropic plasma etching is used to form the via holes, such as via hole 2. Now as shown in FIG. 4, after the via holes are etched, the photoresist mask 30 is removed by plasma ashing in oxygen. Unfortunately, portions 16' of the low k polymer 16 (or SOG) exposed in the via holes to the oxygen plasma are damaged, resulting in a porous, strained layer that is very hygroscopic, which can absorb moisture (H.sub.2 O) and degrade (corrode) the metal plugs that are later formed in the via holes for the next level of metal interconnections.
One common method of circumventing this exposure problem with low k polymer (or SOG) is a partial etch back method in which the low k polymer 16 is etched or polished back to the barrier layer 17 on the metal lines 14, and then th e second CVD silicon oxide insulat ing layer 18 is deposited. The via holes are etched in layers 18 and 17, thereby preventing exposure of the low k polymer or SOG, as depicted in FIG. 5. However, the process is more complex and the advantage of using the low k polymer layer between metal levels to lower interlevel capacitance C2 is lost.
Several methods for forming planarized interconnections using SOG as the intermetal dielectric (IMD) have been described. For example, Sayka U.S. Pat. No. 5,472,825, describes a SOG etch back method similar to the prior art shown in FIG. 5, but does not address the damage problem of a low k polymer or SOG in a non-etch back method. Another method for forming multilayer interconnections and insulating layers is described by Nagata, U.S. Pat. No. 5,082,801, in which a barrier/electromigration layer is formed on the patterned first metal layer (Al) and then patterned to reduce stress around the via hole that is later made in the overlying insulating layer, but Nagata does not address nor use a low k polymer or SOG layer for reduced RC delay time or planarization.
Therefore there is still a strong need in the semiconductor industry for providing a simple non-etch back method for forming damage free low k intermetal dielectric (IMD) layers or SOG on multilevel metal interconnections with reduces inter- and intralevel capacitance and improve reliability.